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Working with ARM exceptions
32
NS7520 Hardware Reference, Rev. D 03/2006
Summary of ARM exceptions
The ARM processor can be interrupted by any of seven basic exceptions:
Reset exception. After a reset condition, the ARM7TDMI saves the current
values of the PC (program counter) and CPSR (Current Processor Status
register).
Undefined exception. The ARM7TDMI takes the undefined instruction trap
when it finds an instruction it cannot handle.
SWI instruction. The ARM7TDMI uses the software interrupt instruction
(SWI) to enter supervisor mode, usually to request a specific supervisor
instruction.
Abort exception. An abort exception indicates that the current memory
access cannot be completed. There are two types of abort exception:
– Prefetch. Occurs during an instruction prefetch.
– Data. Occurs during a data operand access.
IRQ. An interrupt request (IRQ) exception is a normal interrupt serviced by
the ARM7TDMI controller.
FIRQ. A fast interrupt request (FIRQ) exception supports a data transfer or
channel process. An FIRQ interrupt is generated only by the GEN module
timers and watchdog timer.
Exception priorities
Several exceptions can occur at the same time. If this happens, a fixed-priority
system determines the order in which they are handled:
Highest priority
1 Reset
2 Data abort
3 FIRQ
4 IRQ
5 Prefetch abort
6 Undefined instruction, SWI
Lowest priority