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159
Ethernet Module
Bits Access Mnemonic Reset Description
D31 R/W ERX 0 Enable receive FIFO
0 Disables inbound data flow and resets the FIFO
1 Enables inbound data flow
Set to 1 to allow data to be received from the MAC
receiver.
Set to 0 (clear) to reset the receive side FIFO.
D30 R/W ERXDMA 0 Enable receive DMA
0 Disables inbound DMA data request
1 Enables inbound DMA data request
Set to 1 to allow the EFE module to issue receive
data move requests to the DMA controller.
Clear this bit to temporarily stall receive side
Ethernet DMA.
D29 R/W ERXLNG 0 Accept long (>1520 bytes [MAXF setting])
receive packets
When set to 1, allows the MAC to accept packets
that are larger than 1520 bytes.
D28 R/W ERXSHT 0 Accept short (<60 bytes) receive packets
When set to 1, allows the MAC to accept packets
that are smaller than 60 bytes.
The ERXSHT bit is used primarily for debugging.
D27 R/W ERXREG 0 Enable Receive Data register ready interrupt
Set to 1 to generate an interrupt when data is
available in the RX FIFO.
D26 R/W ERFIFOH 0 Enable receive data FIFO half full interrupt
Set to 1 to generate an interrupt when the RX FIFO
is at least half full (1024 bytes).
D25 R/W ERXBR 0 Enable receive buffer ready interrupt
Set to 1 to generate an interrupt when a new data
packet is available in the RX FIFO.
Table 53: Ethernet General Control register bit definition