Filter
Top Products
www.digi.com
65
GEN Module
D18 R/W BME 0 Bus monitor enable
0 Disable bus monitor operation
1 Enable bus monitor operation
Required to avoid a system lockup condition that
can occur when a bus master tries to address
memory space that is not decoded by any
peripheral.
The bus monitor timer detects when a bus master
is accessing a peripheral and there is no transfer
acknowledge (TA_) response. When the bus
monitor timer expires, the current bus cycle is
terminated immediately and the current system
bus master is issued a data abort indicator.
D17:16 R/W BMT 0 Bus monitor timer
Controls the timeout period for the bus monitor
timer:
00 128 BCLKs (bus clocks)
01 64 BCLKS
10 32 BCLKS
11 16 BCLKS
The BMT field generally is set to its maximum
value, but can be set to a lower value to minimize
the latency when issuing a data abort signal. The
BMT field needs to be set to a value that is larger
than the anticipated longest access time for all
peripherals.
D15 R/W USER 0 Enable access to internal chip registers in CPU
user mode
Controls whether applications operating in ARM
user mode (rather than supervisor mode) can
access internal registers within the NS7520.
If set to 0, and an application, operating in
ARM user mode tries to access (read or write)
an internal NS7520 register, the application
receives a data abort. This causes a transfer
in control to the data abort handler.
If set to 1, any application can access the
NS7520 internal registers.
Bits Access Mnemonic Reset Description
Table 24: System Control register bit definition