Filter
Top Products
EFE configuration
194
NS7520 Hardware Reference, Rev. D 03/2006
MII Management Address register
Address: FF80 0428
Register bit assignment
Bits Access Mnemonic Reset Description
D31:13 N/A Reserved N/A N/A
D12:08 R/W DADR 0 MII PHY device address
Represents the 5-bit PHY device address field for
management cycles. Up to 31 different PHY
devices can be addressed; address 0 is reserved.
D07:05 N/A Reserved N/A N/A
D04:00 R/W RADR 0 MII PHY register address
Represents the 5-bit PHY register address field for
management cycles. Up to 32 registers within a
single PHY device can be addressed.
Table 72: MII Management Address register bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved RADR
DADR Reserved