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Serial Channel registers
232
NS7520 Hardware Reference, Rev. D 03/2006
D26 R/W RCGT 0 Enable receive character GAP timer
Detects the maximum allowed time from when
the last byte is placed into the receive data
buffer and when the receive data buffer us
closed.
When RCGT is set to 1, the CGAP field in
Serial Channel Status Register A is set when
the timeout value defined in the Receive Buffer
Character Timer register has expired.
D25:22 N/A Reserved N/A N/A
D21:20 R/W MODE 0 SCC mode
00 UART mode
01 Reserved
10 SPI master mode
11 SPI slave mode
Configures the serial channel to operate in
UART or SPI modes. The MODE field must be
established before the CE bit in Serial Channel
Control Register A is set to 1.
D19 R/W BITORDR 0 Bit ordering
0 Normal; transmit/receive LSB (least
significant bit) first
1 Reverse; transmit/receive MSB (most
significant bit) first
Controls the order in which bits are
transmitted and received in the Serial Shift
register.
When BITORDR is set to 0, the bits are
processed LSB first, MSB last.
When BITORDR is set to 1, the bits are
processed MSB first, LSB last.
D18:16 N/A Reserved N/A N/A
Bit Access Mnemonic Reset Description
Table 88: Serial Channel Control Register B bit definition