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MEM module configuration
100
NS7520 Hardware Reference, Rev. D 03/2006
D01 R/W OE CTRL_ 0 Read cycle mode
0Operate in OE controlled mode; the
memory peripheral operates in a mode
in which the OE_ signal is asserted
after, and negated while, CS[4:0]_ is
asserted.
1Operate in CS controlled mode; the
memory peripheral operates in a mode
in which the OE_ signal is asserted
before, and negated after, CS[4:0]_ is
asserted
Controls the access timing of the OE_ and
CS[4:0]_ signals for non-DRAM memory
peripherals. This bit is used only when the
DRSEL bit is set to 0.
When set to 1, during burst operation, there
are no transitions on CS[4:0] or OE_
between single transfers with a burst.
D00 R/W WE CTRL_ 0 Write cycle mode
0Operate in WE controlled mode; the
memory peripheral operates in a mode
in which the WE_ signal is asserted
after, and negated while, CS[4:0]_ is
asserted.
1Operate in CS controlled mode; the
memory peripheral operates in a mode
in which the WE_ signal is asserted
before, and negated after, CS[4:0]_ is
asserted.
Controls the access timing of the WE_ and
CS[4:0]_ signals for non-DRAM memory
peripherals. This bit is used only when the
DRSEL bit is set to 0.
When set to 1, during burst operation, there
are no transitions on CS[4:0]_ or WE_
between single transfers with a burst.
Bits Access Mnemonic Reset Description
Table 38: Chip Select Option Register A bit definition