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NS7520 DRAM address multiplexing
106
NS7520 Hardware Reference, Rev. D 03/2006
When a particular DRAM has less than 14 address bits, use the lower order NS7520
address bits and leave the upper NS7520 address bits disconnected. The SDRAM bank
select pins must always be connected to the upper order NS7520 address pins.
Note:
Never connect a bank select pin to one of the multiplexed address pins
(A[13:0]).
The NS7520 supports two modes of internal address multiplexing: MODE 0 and
MODE 1. The internal address multiplexing mode is configured using the DMUXM bit in
the Chip Select Base Address register. Each chip select can be configured for a
different address multiplexing mode.
Note:
SDRAM requires MODE 1 multiplexing.
The next two tables show how the NS7520 multiplexes the logical address signal
through the physical address signals during RAS and CAS timeframes. Table 40 applies
to Mode 0; Table 41 applies to Mode 1.
The top row of the table identifies the physical address connection on the
NS7520 devices.
The DRAM row identifies the physical address connection used on the DRAM
device.
The RAS row identifies the “logical” address driven by the NS7520 during
the RAS portion of the RAS/CAS address multiplexing sequence.
The CAS row identifies the “logical” address driven by the NS7520 during
the CAS portion of the RAS/CAS multiplexing sequence.
Note that during the CAS portion of mux mode 1, the A13, A12, and A11 signals are
always driven to 0. These signals must never be connected to the SDRAM bank select
pins. The SDRAM bank select pins must remain stable throughout the entire memory
cycle. If the bank select pins are attached to any of the multiplexed address pins, the
SDRAM part fails because the bank select pins are changing state in the middle of the
memory cycle.
Note:
When using synchronous DRAM, A10 of the SDRAM device must always
connect to CAS0_ of the NS7520. See "SDRAM," beginning on page 111, for
more information.