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33
Working with the CPU
Not all exceptions can occur at the same time, however.
Undefined instructions and SWIs are mutually exclusive, as they each
correspond to particular (non-overlapping) decoding of the current
instruction.
If a data abort occurs at the same time as FIRQ and the FIRQ is enabled
(that is, the CPSR F flag is clear), the data abort takes priority. ARM7TDMI
enters the data abort handler and immediately goes to the FIRQ vector. A
normal return from FIRQ causes the data abort handler to resume
execution.
Placing data abort at a higher priority than FIRQ is necessary to ensure
that the transfer error does not escape detection. The time for this
exception entry should be added to worst-case FIRQ latency
calculations.
Exception vector table
All exceptions result in the ARM processor vectoring to an address in low memory,
using the exception vector table. The exception vector table always exists and always
starts at base address 0.
Vector
address
Vector Description
’h0 RESET Reset vector; for initialization and startup
’h4 Undefined Undefined instruction encountered
’h8 SWI Software interrupt; used for entry point into the kernel
’hC Abort (prefetch) Bus error (no response or error) fetching instructions
’h10 Abort (data) Bus error (no response or error) fetching data
’h14 Reserved Reserved
’h18 IRQ Interrupt from ARM7TDMI interrupt controller
’h1C FIRQ Fast interrupt from ARM7TDMI controller
Table 17: Exception vector table