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Serial Channel registers
236
NS7520 Hardware Reference, Rev. D 03/2006
Register bit assignment
Bits Access Mnemonic Reset Description
D31
D30
D29
D28
R
R
R
R
MATCH1
MATCH2
MATCH3
MATCH4
0
0
0
0
Character Match1
Character Match2
Character Match3
Character Match4
Set when a MATCH character is configured in
the Receive Match register at the same time
the enable receive data match bit is set in
Serial Channel Control Register B. The MATCH
bit indicates that a data match was found in
the receive data stream, and the current
receive data buffer has been closed. The last
character in the receive data buffer contains
the actual MATCH character.
When the receiver is configured for DMA
operation, the MATCH status bits are written
automatically to the DMA receive buffer
descriptor’s status field. When not using
DMA, the MATCH fields are valid only while
the RBC bit in this register is set.
Table 89: Serial Channel Status Register A bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
DSR
RBRK
TRDY
BGAP CGAP Reserved RXFDB CTSDCD RI
DSRI THALF
MATCH
1234
RFE RPE ROVER RRDY RHALF RBC RFULL
DCDI
RII CTSI TBC
T
EMPTY