Filter
Top Products
EFE configuration
176
NS7520 Hardware Reference, Rev. D 03/2006
D12 R RXBR 0 Receive broadcast packet
Set to 1 to indicate that the next packet in the
receive FIFO is a broadcast packet.
When this bit is set, the RXREGR and RXFIFOH bits
in the Ethernet General Status register become
active and the packet can be emptied (using
interrupts, polling, or DMA). When the packet has
been emptied, RXREGR and RXFIFOH become
inactive until the next receive buffer is ready.
D11 R RXMC 0 Receive multicast packet
Set to 1 to indicate that the next packet in the
receive FIFO is a multicast packet.
When this bit is set, the RXREGR and RXFIFOH bits
in the Ethernet General Status register become
active and the packet can be emptied (using
interrupts, polling, or DMA). When the packet has
been emptied, RXREGR and RXFIFOH become
inactive until the next receive buffer is ready.
D10 R RXCRC 0 Receive packet has CRC error
Set to 1 to indicate that the next packet in the
receive FIFO was received with a CRC error.
When this bit is set, the RXREGR and RXFIFOH bits
in the Ethernet General Status register remain
inactive. The bad receive packet is flushed
immediately from the FIFO.
D09 R RXDR 0 Receive packet has dribble bit error
Set to 1 to indicate that, at the end of the next
packet in the receive FIFO, an additional 1 to 7 bits
of data (dribble nibble) were received.
Note: This packet is considered valid if the
RXCRC bit (D10) is not set.
When this bit is set, the RXREGR and RXFIFOH bits
in the Ethernet General Status register remain
inactive. The bad receive packet is flushed
immediately from the FIFO.
Bits Access Mnemonic Reset Description
Table 59: Ethernet Receive Status register bit definition