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179
Ethernet Module
Register bit assignment
Bits Access Mnemonic Reset Description
D31:16 N/A Reserved N/A N/A
D15 R/W SRST 1 Soft reset
Must be set before/while changing any other MAC
bits, and cleared after they are modified. Setting
this bit puts all MAC modules within the MAC
block into reset mode, with the exception of the
host interface. The host interface can be reset only
by a hardware reset condition.
D14 R/W SIMRST 0 Simulation reset
Set to 1 to reset the random number generator
within the MAC transmitter.
D13:12 N/A Reserved N/A N/A
D11 R/W RPEMCSR 0 Reset PEMCS/RX
Set to 1 to reset the MAC control sublayer/receive
domain logic.
D10 R/W RPERFUN 0 Reset PERFUN
Set to 1 to reset the MAC receive function logic.
D09 R/W RPEMCST 0 Reset PEMCS/TX
Set to 1 to reset the MAC control sublayer/transmit
domain logic.
D08 R/W RPETFUN 0 Reset PETFUN
Set to 1 to reset the MAC transmit function logic.
D07:05 N/A Reserved N/A N/A
D04 R/W LOOPBK 0 Internal loopback
1 The MAC transmit interface loops back to the
MAC receive interface.
0 (clear) Normal operation.
D03 R/W TXFLOW 0 TX flow control
1 Allows the MAC to transmit PAUSE flow
control frames
0 Blocks PAUSE flow control frame transmission
Table 60: MAC Configuration Register 1 bit definition