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195
Ethernet Module
MII Management Write Data register
Address: FF80 042C
Register bit assignment
Bits Access Mnemonic Reset Description
D31:16 N/A Reserved N/A N/A
D15:00 R/W MWTD N/A MII write data
When this register is written, an MII management
write cycle is performed using the 16-bit data
defined in the PHY Address register by the
preconfigured PHY device and PHY register
addresses. The write operation is completed when
the BUSY bit in the MII Indicators register (see
page 197) returns to 0.
Table 73: MII Management Write Data register bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
MII write data