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17
Pinout and Packaging
Signal descriptions
CS0_ D5 O 4 Chip select (boot select)
CAS3_ A1 O 4 FP/EDO DRAM column strobe
D31:D24/SDRAM RAS_
CAS2_ C4 O 4 FP/EDO DRAM column strobe
D23:D16/SDRAM CAS_
CAS1_ B3 O 4 FP/EDO DRAM column strobe
D15:D08/SDRAM WE_
CAS0_ A2 O 4 FP/EDO DRAM column strobe
D07:D00/SDRAM A10(AP)
WE_ C6 O 4 Write enable for NCC Ctrl’d cycles
OE_ B6 O 4 Output enable for NCC Ctrl’d cycles
Mnemonic Signal Description
CS0_
CS1_
CS2_
CS3_
CS4_
Chip select 0
Chip select 1
Chip select 2
Chip select 3
Chip select 4
Unique chip select outputs supported by the
NS7520. Each chip select can be configured to
decode a portion of the available address space
and can address a maximum of 256 Mbytes of
address space. The chip selects are configured
using registers in the memory module.
A chip select signal is driven low to indicate the
end of the current memory cycle. For FP/EDO
DRAM, these signals provide the RAS signal.
Table 5: Chip select controller signal description
Symbol Pin I/O OD Description
Table 4: Chip select controller pinout