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MEM module configuration
96
NS7520 Hardware Reference, Rev. D 03/2006
D01 R/W WP 0 Write-protect the chip select
Prevents any bus master from writing to
the memory device. When set to 1, all
memory write-cycles are terminated
immediately with a data-abort indicator.
The WP bit can protect non-volatile
memory devices such as flash and
EEPROM.
D00 R/W V 0 Valid bit
Enables the chip select. When set to 1,
the memory controller uses the fields in
the Chip Select Base Address and Chip
Select Option registers to control the
behavior of the peripheral memory cycles.
Note: It is important that you set the V
bit last, after all other bits in the
MMCR, Chip Select Base
Address, and both Chip Select
Option registers are set.
Bits Access Mnemonic Reset Description
Table 37: Chip Select Base Address register bit definition