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chip select address range 88
Chip Select Base Address register 88, 93
chip select controller
pinout 16
signal descriptions 17
Chip Select Option register 88
Chip Select Option Register A 97
Chip Select Option Register B 101
circular buffer 127, 130
CLKS field settings 192
Collision Window/Collision Retry
register 186
configuration
BSIZE 118
DMA 134
EFE 156
external DMA 146
GEN module 62
MEM module 88
PORTA 75
PORTC 78
serial module 223
x16 SDRAM 113
x32 SDRAM 112
x8 SDRAM 115
CPU
address map 45
core 2
performance 30
working with 29
-
41
D
DACK_ signal 145, 146
data abort exception 32, 35
DC characteristics 262
-
265
absolute maximum ratings 265
input 263
outputs 263
recommended operating
conditions 262
demand-paged virtual memory system 36
DMA buffer descriptor 130
-
132
DMA channel assignments 133
DMA Control register 136
DMA controller 2, 128
DMA controller arbiter 128
DMA interrupts 40
DMA module 127
-
147
buffer descriptor 130
-
132
Buffer Descriptor Pointer register 136
channel assignments 133
configuration 134
controller 128
controller reset 147
DMA Control register 136
Ethernet receiver considerations 145
Ethernet transmitter
considerations 144
external configuration 146
external peripheral support 145
-
147
fly-by transfers 128
memory-to-memory operation 129
Status/Interrupt Enable register 142
DMA Status/Interrupt Enable register 142
DMUXS bit 109
DONE_ signal 145, 146
DRAM address multiplexing 105
-
109
external multiplexer 108
internal multiplexer 105
DRAM refresh 109
DREQ_ signal 145, 146