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Ethernet Module
D19 R/W ETXREG 0 Enable Transmit Data register ready interrupt
Set to 1 to generate an interrupt when the TX FIFO
is ready to accept data.
D18 R/W ETFIFOH 0 Enable transmit data FIFO half empty interrupt
Must be set to 1 to generate an interrupt when the
TX FIFO is at least half empty (<256 bytes).
D17 R/W ETXBC 0 Enable transmit buffer complete interrupt
Set to 1 to generate an interrupt when the transmit
packet transmission is complete.
D16 R/W EFULLD 0 Enable full-duplex operation
Set to 1 to allow the Ethernet TX and RX DMA
operations to operate simultaneously. This bit must
be set when the Ethernet link negotiation results in
full-duplex mode.
It is recommended that you limit transmit frames to
512 bytes when full-duplex operation is enabled.
D15:14 R/W MODE 0 Ethernet interface mode
00 10/100 Mbps MII mode
10 10 Mbps Level 1 ENDEC mode
11 10 Mbps SEEQ ENDEC mode
Identifies the type of Ethernet PHY attached to the
NS7520.
In ENDEC SEEQ mode, the LPBK pin is inverted
before driving the MDC pin.
In ENDEC Level 1 mode, the PDN signal is driven
using an open-drain output driver.
D13 N/A Reserved N/A Reads as zero.
D12 R/W RXCINV 0 Invert the receive clock input
Set to 1 only when the external Ethernet PHY
generates a clock that is inverted in phase relative
to what the MAC is expecting.
This bit is not required for most commercially
available PHY devices.
Bits Access Mnemonic Reset Description
Table 53: Ethernet General Control register bit definition