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Working with ARM exceptions
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NS7520 Hardware Reference, Rev. D 03/2006
All internal ARM7TDMI internal peripherals are presented to the CPU using the IRQ or
FIRQ interrupt inputs. The ARM can mask various ARM7TDMI peripheral interrupts at
the global level, using the ARM7TDMI interrupt controller. The ARM also can mask
interrupts at the micro-level, using configuration features with the peripheral
modules.
All IRQ interrupts are disabled when the I bit is set in the ARM CPSR. When the I bit is
cleared, those interrupts enabled in the ARM7TDMI interrupt controller can assert the
IRQ input to the ARM processor.
The ARM processor sets the I bit automatically when entering an interrupt service
routine (ISR), which disables recursive interrupts. The ISR’s first task is to read the
Interrupt Status register, which identifies all active sources for the IRQ interrupt.
Firmware sets the priorities for servicing interrupts at bootup, using the bits defined
in the Interrupt Status register.
Detail of ARM exceptions
Reset exception
A reset exception is the highest priority exception. When the ARM7TDMI is held in
reset, the processor abandons the executing instruction and continues to fetch
instructions from incrementing word addresses.
When the ARM7TDMI is removed from reset, the processor performs these steps:
1 Overwrites R14_svc and SPSR_svc (Saved Processor Status register) by copying the
current values of the PC and CPSR into them. The values of the saved PC and
SPSR are not defined.
2 Forces the CPSR M field to 10011 (supervisor mode), sets the I and F bits in the
CPSR, and clears the CPSR T bit (back to ARM mode).
3 Forces the PC to fetch the next instruction from address ’h00.
4 Resumes execution in ARM state.
Undefined exception
When the ARM7TDMI encounters an instruction it cannot handle, it takes the
undefined instruction trap. The undefined instruction trap can extend either the
Thumb or ARM instruction set by software emulation.