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EFE configuration
166
NS7520 Hardware Reference, Rev. D 03/2006
D24 R/W RXSKIP 0 Receive buffer skip
Used (written) instead of clearing the RXBR bit.
Writing to RXSKIP clears the RXBR bit and flushes
the next available packet from the receive FIFO.
Using RXSKIP is a means of performing receive
packet filtering in the interrupt service routine; the
packet simply is flushed from the FIFO rather than
read out of the FIFO.
D23:20 N/A Reserved N/A N/A
D19 R TXREGE 0 Transmit register empty
Set to 1 whenever the transmit FIFO is ready to
accept data. When active high, this bit can cause
an interrupt when the ETXREGE bit is also set (in
the Ethernet General Control register).
TXREGE is never active when TXBC (D17) is set;
TXBC must be cleared to activate TXREGE.
D18 R TXFIFOH 0 Transmit FIFO half empty
Set to 1 when the transmit FIFO is at least half
empty.
When active high, this bit can cause an interrupt
when the ETFIFOH bit is also set (in the Ethernet
General Control register).
D17 R/C TXBC 0 Transmit buffer complete
Set when packet transmission is complete. When
active high, this bit can cause an interrupt when
the EXTBC bit is also set (in the Ethernet General
Control register).
The TXBC bit indicates to the interrupt service
routine to read the Ethernet Transmit Status
register. After the Ethernet Transmit Status
register is read, clear the TXBC bit by writing a 1
to the TXBC bit position in this (Ethernet General
Status) register. After TXBC is cleared, the
TXREGE and TXFIFOH bits become active.
D16 R TXFIFOE 1 Transmit FIFO empty
Active (set to 1) when the transmit FIFO is empty.
Bits Access Mnemonic Reset Description
Table 55: Ethernet General Status register bit definition