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63
GEN Module
GEN module registers
All registers are 32 bits unless otherwise noted.
System Control register
Address: FFB0 0000
General information
All bits in the System Control register are active high unless an underscore (_)
appears in the signal name; the underscore indicates active low.
Register bit assignment
Bits Access Mnemonic Reset Description
D31 R/W LENDIAN
ADDR27
Configure chip to run in Little Endian mode
Controls the Endian configuration for the NS7520.
1 Configures the chip to operate in Little Endian
mode
0 Configures the chip for Big Endian mode
D30:29 N/A Reserved N/A Initialized to and always read as 10 (full speed).
Table 24: System Control register bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
BCLKD SWE SWRI SWT N/A BME BMT
LEND-
IAN
Reserved
Reserved
USER BUSER Rsvd
DMA
TST
TEA
LAST
MIS
ALIGN
Reserved
CPU
DIS
DMA
RST
BSYNC Reserved