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Working with the CPU
Entering and exiting an exception (software action)
The ARM7TDMI performs specific steps when handling exceptions.
Entering an exception
When handling an exception, ARM7TDMI does this:
1 Preserves the address of the next instruction in the appropriate Link register.
– If the exception has been entered from the ARM state, the address of the
next instruction is copied into the Link register. The address is either
current
PC + 4 or PC + 8, depending on the exception. (See Table 18:
"Exception entry/exit by exception type" on page 38.)
– If the exception has been entered from Thumb state, the value written into
the Link register is the current PC offset by a value that lets the program
continue from the correct place on return from the exception.
The exception handler does not need to determine from which state the
exception was entered. With an SWI, for example,
MOVS PC, R14_SVC always
returns to the next instruction whether executed in ARM or Thumb state.
2 Copies the CPSR into the appropriate SPSR.
3 Forces the CPSR mode bits to a value that depends on the exception.
4 Forces the PC to fetch the next instruction from the relevant exception vector.
5 Sets the I (for IRQ interrupts) or F (for FIRQ interrupts) bits to disable interrupts
to prevent unmanageable nesting of exceptions.
Note:
If the processor is in Thumb state when an exception occurs, it
automatically switches into ARM state when the PC is loaded with the
exception vector address.
Exiting an exception
On completion, ARM7TDMI does this:
1 Moves the Link register, minus the offset where appropriate, to the PC. The
offset value varies depending on the type of exception.
2 Copies the SPSR back to the CPSR.
3 Clears the interrupt disable flags, if they were set on entry.