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Serial Controller Module
D10 R RHALF 0 Receive FIFO half-full interrupt pending
Indicates that the receive data FIFO contains
at least 16 bytes. RHALF typically is used only
in interrupt-driven applications; it is not used
for DMA operation.
The RHALF status condition can be
programmed to generate an interrupt by
setting the related IE bit in Serial Channel
Control Register A.
D09 R/C RBC 0 Receive buffer closed interrupt pending
Indicates a receive buffer closed condition.
Once set, the RBC bit remains set until
acknowledged. RBC is acknowledged by
writing a 1 to this same bit position in this
register. The RBC bit is acknowledged
automatically by hardware when the receiver
is configured to operate in DMA mode. The
RBC status condition can be programmed to
generate an interrupt by setting the related IE
bit in Serial Channel Control Register A.
The RBC field indicates that bits D31:26 in this
register are valid. While the RBC field is active,
the RRDY field is not. To activate RRDY (to
read the data FIFO), the RBC bit must be
acknowledged. This interlock between RBC
and RRDY allows the firmware driver to read
the D31:26 status bits. When operating in
DMA mode, the status bits are written
automatically to the receive DMA buffer
descriptor, and the interlock between RBC and
RRDY is handled automatically in the
hardware.
D08 R RFULL 0 Receive FIFO full
Indicates that the receive data FIFO currently
is full.
Bits Access Mnemonic Reset Description
Table 89: Serial Channel Status Register A bit definition