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Serial Channel registers
254
NS7520 Hardware Reference, Rev. D 03/2006
These bit rate examples are generated by a bit-rate generator using an 18.432 MHz
quartz crystal.
Serial Channel 1, 2 FIFO registers
Address: FFD0 0010 / 50
The serial channel FIFO data registers manually interface with the serial controller
FIFOs instead of using DMA support.
Writing to this register loads the transmit FIFO. This register can be written only
when the TRDY bit is set in Serial Channel Status Register A. Writing to the Serial
Channel FIFO register automatically clears the TRDY bit.
N register
Bit rate CLKMUX X1 mode X8 mode X16 mode
75 00 N/A N/A 1535
150 00 N/A N/A 767
300 00 N/A N/A 383
600 00 N/A N/A 191
1200 00 1535 N/A 95
2400 00 767 N/A 47
4800 00 383 N/A 23
7200 00 255 N/A 15
9600 00 191 N/A 11
14400 00 127 N/A 7
19200 00 95 N/A 5
28800 00 63 N/A 3
38400 00 47 N/A 2
57600 00 31 N/A 1
115200 00 15 N/A 0
230400 00 N/A 0 N/A
Table 91: Bit rate examples