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Serial Channel registers
240
NS7520 Hardware Reference, Rev. D 03/2006
D12 R/C ROVER 0 Receive overrun interrupt pending
Indicates that a receive overrun error condition
has been found. An overrun condition
indicates that the FIFO was full while data
needed to be written by the receiver. When
the FIFO is full, any new receive data will be
discarded; the contents of the FIFO before the
overrun condition remains the same.
Once set, the ROVER field remains set until
acknowledged. ROVER is acknowledged by
writing a 1 to this same bit position in this
register.
The ROVER status condition can be
programmed to generate an interrupt by
setting the related IE bit in the Serial Channel
Control Register A.
D11 R RRDY 0 Receive register ready interrupt pending
Indicates that data is available to be read from
the FIFO Data register. Before reading the FIFO
Data register, the RXFDB field in this register
must be read to determine how many active
bytes are available during the next read of the
FIFO Data register. RRDY typically is used only
in interrupt-driven applications; it is not used
for DMA operation. The RRDY status condition
can be programmed to generate an interrupt
by setting the related IE bit in Serial Channel
Control Register A.
RRDY is never active while RBC is active. The
RBC bit must be acknowledged to activate
RRDY. When the receiver is configured to
operate in DMA mode, the interlock between
RBC and RRDY is handled automatically in
hardware.
Bits Access Mnemonic Reset Description
Table 89: Serial Channel Status Register A bit definition