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EFE configuration
160
NS7520 Hardware Reference, Rev. D 03/2006
D24 R/W ERXBAD 0 Accept bad receive packets
When set to 1, allows the MAC to accept packets
received in error. Bad receive packets include those
packets with CRC errors, alignment errors, and
dribble errors.
The ERXBAD bit is used primarily for debugging.
D23 R/W ETX 0 Enable transmit FIFO
0 Disables outbound data flow and resets the
FIFO
1 Enables outbound data flow
Set to 1 to allow data to be written to the TX FIFO.
Clear to reset the transmit side FIFO.
D22 R/W ETXDMA 0 Enable transmit DMA
0 Disables outbound DMA data request
1 Enables outbound DMA data request
Set to 1 to allow the EFE module to issue transmit
data move requests to the DMA controller.
Clear this bit to temporarily stall transmit side
Ethernet DMA.
Do not set this bit when operating the Ethernet
receiver in interrupt service mode.
D21:20 R/W ETXWM 0 Transmit FIFO water mark before transmit start
00 25% FIFO full
01 50% FIFO full
10 75% FIFO full
11 Reserved
Identifies the minimum number of bytes required in
the transmit FIFO to initiate packet transmission. A
larger watermark setting increases transmit packet
latency, allowing for more slack in the memory
system FIFO fill rate.
Note that packet transmission can also be initiated
using DMA (see "Ethernet transmitter
considerations" on page 144) and the FIFO Data
register (see "Ethernet FIFO Data register" on page
167).
Bits Access Mnemonic Reset Description
Table 53: Ethernet General Control register bit definition