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Serial Channel registers
242
NS7520 Hardware Reference, Rev. D 03/2006
D07 R/C DCDI 0 Change in DCD interrupt pending
Indicates a state change in the EIA data carrier
detect signal. Once set, the DCDI field remains
set until acknowledged. DCDI is
acknowledged by writing a 1 to this same bit
position in this register.
The DCDI status condition can be programmed
to generate an interrupt by setting the related
IE bit in Serial Channel Control Register A.
D06 R/C RII 0 Change in RI interrupt pending
Indicates a state change in the EIA ring
indicator signal. Once set, the RII bit remains
set until acknowledged. RII is acknowledged
by writing a 1 to this same bit position in this
register.
The RII status condition can be programmed to
generate an interrupt by setting the related IE
bit in Serial Channel Control Register A.
D05 R/C DSRI 0 Change in DSR interrupt pending
Indicates a state change in the EIA data set
ready signal. Once set, the DSRI bit remains
set until acknowledged. DSRI is acknowledged
by writing a 1 to this same bit position in this
register.
The DSRI state condition can be programmed
to generate an interrupt by setting the related
IE bit in Serial Channel Control Register A.
D04 R/C CTSI 0 Change in CTS interrupt pending
Indicates a state change in the EIA clear to
send signal. Once set, the CTSI bit remains set
until acknowledged. CTSI is acknowledged by
writing a 1 to this same bit position in this
register.
The CTSI state condition can be programmed
to generate an interrupt by setting the related
IE bit in Serial Channel Control Register A.
Bits Access Mnemonic Reset Description
Table 89: Serial Channel Status Register A bit definition