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FP/EDO DRAM controller
110
NS7520 Hardware Reference, Rev. D 03/2006
Normal and burst (FP/EDO) cycles
Programmable wait states for normal (also first cycle ion burst access) and
burst cycles
Programmable base address and chip select size
Single cycle read/write
Figure 9 shows FP DRAM normal read and write cycles.
Figure 9: Normal FP DRAM bus cycles
All DRAM cycles must operate a minimum of 1 wait state. (If the controller is
programmed for 0 wait states, operation is unpredictable). A single wait state DRAM
cycle requires the DRAM devices to tolerate a single BCLK cycle for RAS precharge
and CAS access timing.
The CAS_ signal is deasserted on the rising edge in which TA_ is recognized.
The RAS_ signal is deasserted on the falling edge of BCLK after CAS_ is
asserted.
Important:
You cannot set the PS field to 2’b11 for FP DRAM.
T1 TW TW T2 T1 TW TW T2 T1 TW
FP DRAM Write FP DRAM Read
BCLK
ADDR
R/W_
RAS_
DADDR
CAS_
WE_
OE_
DATA
TA_