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Electrical Characteristics
Oscillator Characteristics
Figure 31 illustrates the recommended oscillator circuit details.
Rise/fall time. The max rise/fall time on the system clock input pin is 1.5ns
when used with an external oscillator.
Duty cycle. The duty cycle is system-dependent with an external oscillator.
It affects the setup and hold times of signals that change in the falling clock
edges, such as WE_/OE_.
Recommendation: Use a 3.3V, 50±10% duty cycle oscillator with a 100 ohm
series resistor at the output. The PLLs can handle a 25% duty cycle clock
(minimum high/low time 4.5nS).
Signal Derating (ns/pF)
BCLK 0.069
A[27:0], TS_, TA_, TEA_, BR_, BG_, BUSY_, DATA[31:0] 0.150
BE[3:0] 0.300
CS[4:0]_, CAS[3:0], RW_, WE_, OE_ 0.137
MDC, TXD[3:0], TXER, TXEN, TDO 0.274
Table 101: Output buffer derating by load capacitance