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185
Ethernet Module
Non-Back-to-Back Inter-Packet-Gap register
Address: FF80 040C
Register bit assignment
Bits Access Mnemonic Reset Description
D31:15 N/A Reserved N/A N/A
D14:08 R/W IPGR1 N/A Non back-to-back inter-packet-gap — part 1
A programmable field that represents the optional
carrierSense window (referenced in IEEE 802.3
“Carrier Deference”).
If carrier is found during IPGR1 timing, the MAC
defers to the carrier. If carrier is found after IPGR1
times out, the MAC continues timing IPGR2. The
transmitter causes a collision, activating the
random back off fairness algorithm (ensuring fair
access to the medium).
The range of values for IPGR1 is
’h0—IPGR2.
The default value is
’hC (12d).
D07 N/A Reserved N/A N/A
D06:00 R/W IPGR2 N/A Non-back-to-back inter-packet-gap—part 2
A programmable field that represents the non-
back-to-back inter-packet-gap.
The default setting for IPGR2 is
’h12 (18d), which
represents these minimum IPG values:
In 100 Mbps: 0.96 μs
In 10 Mbps: 9.6 μs
Table 64: Non-Back-to-Back Inter-Packet-Gap register bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
IPGR2IPGR1
Rsvd Rsvd