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169
Ethernet Module
Register bit assignment
Ethernet Transmit Status register
Address: FF80 0010
The Ethernet Transmit Status register contains the status for the last completed
transmit buffer. The transmit buffer complete bit (TXBC) is set in the Ethernet
General Status register when a transmit frame is completed and the Ethernet
Transmit Status register is loaded. The lower 16 bits (D15:00) of the register are also
loaded into the StatusOrIndex field of the DMA buffer descriptor when using DMA
mode.
Register bit assignment
Bits Access Mnemonic Reset Description
D31:00 R/W FIFO N/A FIFO data — FF80 0008
First and middle words
D31:00 R/W FIFO N/A FIFO data — FF80 000C
Last word, write-only
Table 57: Ethernet FIFO Data register bit definition
Bits Access Mnemonic Reset Description
D31:16 N/A Reserved N/A N/A
Table 58: Ethernet Transmit Status register bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Not
used
TXCOLCTXOK TXBR TXMC TXAL
TXA
ED
TXA
EC
TXA
UR
TXAJ
TX
DEF
TX
CRC
Not
used