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GEN module registers
64
NS7520 Hardware Reference, Rev. D 03/2006
D28 R/W BCLKD 0 BCLK output disable
0 BCLK output enabled
1 BCLK output forced to LOW state
Shuts down the operation of the BCLK signal.
Turning off the BCLK signal minimizes electro-
magnetic interference (EMI) when BCLK is not
required for an application.
D27:25 N/A Reserved N/A N/A
D24 R/W SWE 0 Software watchdog enable
Set to 1 to enable the watchdog timer circuit.The
watchdog timer can be configured, using SWRI, to
generate an interrupt or reset condition if and
when the watchdog timer expires. Once SWE is
set to 1, only a hardware reset sets the bit back
to 0.
D23:22 R/W SWRI 0 Software watchdog reset/interrupt select
Controls the action that occurs when the
watchdog timer expires:
00 Software watchdog causes normal (IRQ)
interrupt
01 Software watchdog causes fast (FIRQ)
interrupt
10 Software watchdog causes reset
11 Reserved
D21:20 R/W SWT 0 Software watchdog timeout (in seconds)
Controls the timeout period for the watchdog
timer. The timeout period is a function of F
XTALE
:
00 2
20
/F
XTALE
01 2
22
/F
XTALE
10 2
24
/F
XTALE
11 2
25
/F
XTALE
D19 N/A Reserved N/A N/A
Bits Access Mnemonic Reset Description
Table 24: System Control register bit definition