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Serial Controller Module
D27 R BGAP 0 Buffer GAP timer
Set when the enable receive buffer gap timer
is set in Serial Channel Control Register B and
the timeout value defined in the Receive Buffer
GAP Timer register has expired. This bit
indicates that the maximum allowed time has
occurred since the first byte was placed into
the receive data buffer. The receive data
buffer is closed under this condition.
When the receiver is configured for DMA, the
BGAP bit is written automatically to the DMA
receive buffer descriptor’s status field. When
not using DMA, BGAP is valid only while the
RBC bit in this register is set.
D26 R CGAP 0 Character GAP timer
Set when the enable receive character gap
timer is set in Serial Channel Control Register
B and the timeout value defined in the Receive
Character GAP Timer register has expired. This
bit indicates that the maximum allowed time
has occurred since the previous byte was
placed into the receive data buffer. The
receive data buffer is closed under this
condition.
When the receiver is configured for DMA, the
CGAP bit is written automatically to the DMA
buffer descriptor’s status field. When not
using DMA, CGAP is valid only while the RBC
bit is set in this register.
D25:22 N/A Reserved N/A N/A
Bits Access Mnemonic Reset Description
Table 89: Serial Channel Status Register A bit definition