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Timing Diagrams
274
NS7520 Hardware Reference, Rev. D 03/2006
SRAM burst read (2111)
CS* controlled read (wait = 0, BCYC = 00)
Notes:
1 If the next transfer is DMA, null periods between memory transfers can occur.
Thirteen clock pulses are required for DMA context switching.
2 Port size determines which byte enable signals are active:
– 8-bit port = BE3*
– 16-bit port = BE[3:0]
– 32-bit port = BE[3:0]
3 The TA* and TEA*/LAST signals are for reference only.
T1 T2 T2 T2 T2 Note-1 T1
12
1818
2828
2727
3636
6
3131
3030
11
10
Note-2
BCLK
TA* (Note-3)
TEA* (Note-3)
A[27:0]
BE[3:0]*
CS[4:0]*
read D[31:0]
Sync OE*
CS0OE*
RW*