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191
Ethernet Module
MII Management Configuration register
Address: FF80 0420
Register bit assignment
Bits Access Mnemonic Reset Description
D31:16 N/A Reserved N/A N/A
D15 R/W RMIIM 0 Reset MII management
Set this bit to 1 to reset the MII management
module.
D14:05 N/A Reserved N/A N/A
D04:02 R/W CLKS N/A Clock select
Used by the clock divide logic when creating the
MII management clock (MDC pin). The IEEE
802.3u standard requires that the clock be no
faster than 2.5 MHz. See Table 70: "CLKS field
settings" on page 192 for examples.
Note: Some PHY devices support clock rates up
to 12.5 MHz.
D01 R/W SPRE 0 Suppress preamble
1 The MII management module performs read/
write cycles without the 32-bit preamble field.
0 Normal cycles are performed.
Note: Some PHY devices support suppressed
preamble.
Table 69: MII Management Configuration register bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved
SPRE SCANICLKSRMIIM