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81
GEN Module
Interrupts come from different sources on the chip and are managed with Interrupt
Control registers. Interrupts can be enabled/disabled on a per-source basis using the
Interrupt Enable registers. These registers serve as masks for the different interrupt
sources.
Interrupt controller registers
Address: FFB0 0030 / 0034 / 0038
There are five pairs of registers in the interrupt controller:
Interrupt Enable register. A read/write location for reading and writing all
interrupt enable bits as a typical register.
Interrupt Enable Set/Interrupt Status Enabled registers. Perform two
different functions depending on whether a register is read or written:
– When read, the register indicates the current state of all enabled
interrupts.
– When written, a 1 in a bit position sets that interrupt enable; a 0 in a bit
position has no effect.
Interrupt Enable Clear/Interrupt Status Raw registers. Perform two
different functions depending on whether a register is read or written:
– When read, the register indicates the current state of all interrupts
regardless of the state of the enables.
– When written, a 1 in a bit position clears that interrupt enable; a 0 in a bit
position has no effect.
Register bit assignment
All registers use the same 32-bit layout.
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
DMA1-13 Rsvd
ENET
1 RX
ENET
1 TX
SER
1 RX
SER
1 TX
SER
2 RX
SER
2 TX
Reserved MAC1
Watch
Dog
Timer
1
Timer
2
PORT
C3
PORT
C2
PORT
C1
PORT
C0