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EFE configuration
180
NS7520 Hardware Reference, Rev. D 03/2006
MAC Configuration Register 2
Address: FF80 0404
MAC Configuration Register 2 contains bits that control functionality within the
Ethernet MAC block.
D02 R/W RXFLOW 0 RX flow control
1 The MAC acts on received PAUSE flow control
frames.
0 The MAC ignores all PAUSE flow control
frames.
D01 R/W PALLRX 0 Pass ALL receive frames
1 The MAC receiver indicates PASS CURRENT
RECEIVE FRAME for all frames, no matter the
type (normal or flow control).
0 Deasserts PASS CURRENT RECEIVE FRAME
for valid control frames.
D00 R/W RXEN 0 Receive enable
Set to 1 to allow the MAC receiver to receive
frames.
Internally, the MAC synchronizes this control bit to
the incoming receive stream and outputs
SYNCHRONIZED RECEIVE ENABLE. The host
system uses SYNCHRONIZED RECEIVE ENABLE to
qualify receive frames.
Bits Access Mnemonic Reset Description
Table 60: MAC Configuration Register 1 bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Rsvd
E
DEFER
LONGP
PUREP
CRC
EN
DEL
CRC
HUGE FLENC
BACKP NOBO Reserved AUTOP VLANP
PAD
EN
FULLD