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Working with ARM exceptions
36
NS7520 Hardware Reference, Rev. D 03/2006
The abort mechanism allows the implementation of a demand-paged virtual memory
system. In this type of system, the processor is allowed to generate arbitrary
addresses. When the data at an address is unavailable, the memory management unit
(MMU) signals an abort. The abort handler must then work out the cause of the abort,
make the requested data available, and retry the aborted instruction. The
application program needs no knowledge of the amount of memory available to it,
and its state is not affected by the abort.
The handler executes one of the following instructions, irrespective of the state (ARM
or Thumb), after fixing the cause of the abort:
For a prefetch abort: SUBS PC, R14_abt, #4
For a data abort: SUBS PC, R14_abt, #8
IRQ exception
An IRQ exception is a normal interrupt sourced by the ARM7TDMI interrupt controller.
IRQ has a lower priority than FIRQ, and is masked out when an FIRQ sequence is
entered. IRQ can be disabled at any time by setting the I bit in CPSR to 1; this can be
done only from privileged (non-user) mode.
The IRQ handler should leave the interrupt by executing the following instruction
irrespective of the state (ARM or Thumb):
SUBS PC, R14_irq, #4.
FIRQ exception
An FIRQ exception supports a data transfer or channel process. In ARM state, FIRQ has
enough registers to remove the need for register saving, which minimizes context
switching overhead.
Only two peripherals can generate an FIRQ interrupt: the GEN module built-in timers
and the GEN module watchdog timer.
The FIRQ handler should leave the interrupt by executing the following instruction
irrespective of the state (ARM or THUMB):
SUBS PC, R14_firq, #4.
The FIRQ interrupt can be disabled by setting the CPSR F flag to 1, only in non-user
mode. If the F flag is clear, the ARM7TDMI checks for a low level on the output of the
FIRQ synchronizer at the end of each instruction.