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Serial Controller Module
D20:19 R/W TDCR 0 Transmit divide clock rate
00 1x clock mode (only NRZ or NRZI
allowed)
01 8x clock mode
10 16x clock mode
11 32x clock mode
Determine the oversampling multiplier for the
transmitter and receiver clocks.
If DPLL is not used and you are not using
UART, select the value 1x.
If DPLL is not used but you are using
UART, select 8x, 16x, or 32x (16x is
recommended).
In most applications, the TDCR and RDCR
configurations should match.
When DPLL is used in the application, the
selected TDCR/RDCR value is a function
of the transmitter encoding. NRZ and
NRZI modes can use the 1x configuration;
all other encoding must use 8x, 16x, or
32x configuration mode. 8x configuration
provides the highest data rate; 32x mode
provides the highest resolution.
The TMODE bit in the Serial Channel Bit-Rate
register is maintained for NET+ARM family
backward compatibility. When setting TDCR
or RDCR to a non-zero value, the TMODE must
be set to 1. When the TMODE, TDCR, and
RDCR fields are set to 0, the port defaults to
16x mode of operation.
D18 N/A Reserved N/A N/A
Bits Access Mnemonic Reset Description
Table 90: Serial Channel Bit-Rate register bit definition