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Serial Channel registers
244
NS7520 Hardware Reference, Rev. D 03/2006
Serial Channel 1, 2 Bit-Rate registers
Address: FFD0 000C / 4C
The serial channel bit rate registers configure the bit-rate for each serial channel.
The serial channel can be configured to operate using an internal or external timing
reference. When configured for internal timing, the timing reference is provided by
the bit-rate generator. When configured for external timing, the timing reference is
provided by the PORTC signals RXCLK and TXCLK.
The serial channel can be configured to operate in either 1X (synchronous) mode or
16X (asynchronous) mode. When using the internal bit-rate generator, the frequency
must be configured properly to match the mode being used.
TBC continued The TBC field is set when the last character in
the transmit FIFO has been shifted out of the
shift register and the FIFO currently is empty.
While the TBC field is active, the TRDY bit is
not active. To activate TRDY (to write to the
data FIFO), TBC must be acknowledged. When
operating in DMA mode, the interlock between
TBC and TRDY is handled automatically in
hardware.
D00 R TEMPTY 0 Transmit FIFO empty
Indicates that the transmit data FIFO is
currently empty. TEMPTY simply reports the
status of the FIFO; it does not indicate that the
character currently in the transmit shift
register has been transmitted. The TBC bit
must be used for the all sent condition.
Bits Access Mnemonic Reset Description
Table 89: Serial Channel Status Register A bit definition
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
TX
SRC
CLKM
UX
EBIT
RICS NREG
T
MODE
RX
SRC
RX
EXT
TX
EXT
TXC
INV
RXC
INV
Rsvd TDCR RDCRRsvd
Rsvd TICS RSVD Rsvd