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EFE configuration
172
NS7520 Hardware Reference, Rev. D 03/2006
D09 R TXAUR 0 Transmit aborted — underrun
Set to 1 to indicate that the last Ethernet packet
was not transmitted successfully; packet
transmission was aborted due to a FIFO underrun
condition. A FIFO underrun condition indicates that
the DMA controller was unable to fill the FIFO at a
fast enough rate compared to the rate of
transmission on the Ethernet medium, for one of
these reasons:
The DMA controller was not configured for
bursting.
The memory peripheral device was not
configured for bursting.
The memory peripheral device is too slow to
support the Ethernet interface.
When this bit is set, the transmit frame is flushed
automatically from the transmit FIFO. TXREGE and
TXFIFOH in the Ethernet General Status register
become active when the FIFO is ready to start
receiving the next packet.
TXBC in the Ethernet General Status register
becomes active when TXAUR is set.
D08 R TXAJ 0 Transmit abort — jumbo
Set to 1 to indicate that the last Ethernet packet
was not transmitted successfully; packet
transmission was aborted due to a jumbo
condition. A jumbo condition means that the
packet was too large; that is, greater than 1518
bytes. Packets larger than 1518 bytes are not
transmitted successfully unless the HUGEN bit is
set in the MAC Configuration register.
When this bit is set, the transmit frame is
automatically flushed from the transmit FIFO.
TXREGE and TXFIFOH in the Ethernet General
Status register become active when the FIFO is
ready to start receiving the next packet.
TXBC in the Ethernet General Status register
becomes active when TXAJ is set.
D07 N/A Not used N/A Always set to 0.
Bits Access Mnemonic Reset Description
Table 58: Ethernet Transmit Status register bit definition