Filter
Top Products
NS7520 bootstrap initialization
60
NS7520 Hardware Reference, Rev. D 03/2006
NS7520 bootstrap initialization
Many internal NS7520 features are configured when the RESET pin is asserted. The
address bus configures the appropriate control register bits at powerup. (See also
"External oscillator mode hardware configuration," beginning on page 51.)
Note:
The initial operating bus speed must be selected by adding pulldown to
the address lines that preset the ND value (ADDR[4:0]).
Address bit Name Description
ADDR[27] Endian configuration 0 Little Endian configuration
1 Big Endian configuration
ADDR[26] CPU bootstrap 0 CPU disabled; GEN_BUSER=1
1 CPU enabled; GEN_BUSER=0
ADDR[24:23] CS0/MMCR[19:18] setting 00 8-bit SRAM, 63 wait-states/b00
01 32-bit SRAM, 63 wait-states/b01
10 32-bit SRAM
11 16-bit SRAM, 63 wait-states/b11
ADDR[19:09] GEN_ID setting GEN_ID=A[19:09], Default=
’h3ff
ADDR[8:7] PLL IS setting IS=A[8:7], Default=’b10
ADDR[6:5] PLL FS setting FS=A[6:5], Default=’b00
ADDR[4:0] PLL ND setting ND=A[4:0], Default=’b01011