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S3C2410A MICROPROCESSOR ix
Table of Contents (Continued)
Chapter 6 NAND Flash Controller
Overview.............................................................................................................................................6-1
Features.....................................................................................................................................6-1
Block Diagram ............................................................................................................................6-2
Operation Scheme.......................................................................................................................6-2
Auto Boot Mode Sequence...........................................................................................................6-3
Nand Flash Mode Configuration ....................................................................................................6-3
Nand Flash Memory Timing..........................................................................................................6-3
Pin Configuration.........................................................................................................................6-4
Boot and Nand Flash Configurations..............................................................................................6-4
512-Byte Ecc Parity Code Assignment Table.................................................................................6-4
Nand Flash Memory Mapping.......................................................................................................6-5
Special Function Registers...................................................................................................................6-6
Nand Flash Configuration (NFCONF) Register................................................................................6-6
Nand Flash Command Set (NFCMD) Register................................................................................6-7
Nand Flash Address Set (NFADDR) Register.................................................................................6-7
Nand Flash Data (NFDATA) Register.............................................................................................6-7
Nand Flash Operation Status (NFSTAT) Register ...........................................................................6-8
Nand Flash ECC (NFECC) Register ..............................................................................................6-8
Chapter 7 Clock & Power Management
Overview.............................................................................................................................................7-1
Functional Description .........................................................................................................................7-2
Clock Architecture.......................................................................................................................7-2
Clock Source Selection................................................................................................................7-2
Phase Locked Loop (PLL)............................................................................................................7-4
Clock Control Logic .....................................................................................................................7-6
Power Management.....................................................................................................................7-9
Clock Generator & Power Management Special Register ........................................................................7-19
Lock Time Count Register (LOCKTIME).........................................................................................7-19
PLL Value Selection Table ...........................................................................................................7-20
Clock Control Register (CLKCON).................................................................................................7-21
Clock Slow Control (CLKSLOW) Register......................................................................................7-22
Clock Divider Control (CLKDIVN) Register......................................................................................7-22