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LCD CONTROLLER S3C2410A
15-38
LCD Interrupt Mask Register
Register Address R/W Description Reset Value
LCDINTMSK 0X4D00005C R/W Determine which interrupt source is masked.
The masked interrupt source will not be serviced.
0x3
LCDINTMSK Bit Description Initial state
FIWSEL [2] Determine the trigger level of LCD FIFO.
0 = 4 words 1 = 8 words
INT_FrSyn [1] Mask LCD frame synchronized interrupt.
0 = The interrupt service is available.
1 = The interrupt service is masked.
1
INT_FiCnt [0] Mask LCD FIFO interrupt.
0 = The interrupt service is available.
1 = The interrupt service is masked.
1
LPC3600 Control Register
Register Address R/W Description Reset Value
LPCSEL 0X4D000060 R/W This register controls the LPC3600 modes. 0x4
LPCSEL Bit Description Initial state
Reserved [2] Reserved 1
RES_SEL [1] 1 = 240×320 0
LPC_EN [0] Determine LPC3600 Enable/Disable.
0 = LPC3600 Disable
1 = LPC3600 Enable
0