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CLOCK & POWER MANAGEMENT S3C2410A
7-8
FCLK, HCLK, and PCLK
FCLK is used by ARM920T.
HCLK is used for AHB bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD
controller, the DMA and the USB host block.
PCLK is used for APB bus, which is used by the peripherals such as WDT, IIS, I2C, PWM timer, MMC interface,
ADC, UART, GPIO, RTC and SPI.
The S3C2410A supports selection of Dividing Ratio between FCLK, HLCK and PCLK. This ratio is determined by
HDIVN and PDIVN of CLKDIVN control register.
HDIVN1 HDIVN PDIVN FCLK HCLK PCLK Divide Ratio
0 0 0 FCLK FCLK FCLK 1 : 1 : 1
(Default)
0 0 1 FCLK FCLK FCLK / 2 1 : 1 : 2
0 1 0 FCLK FCLK / 2 FCLK / 2 1 : 2 : 2
0 1 1 FCLK FCLK / 2 FCLK / 4 1 : 2 : 4
(Recommended)
1 0 0 FCLK FCLK / 4 FCLK / 4 1 : 4 : 4
After setting PMS value, it is required to set CLKDIVN register. The setting value of CLKDIVN will be valid after PLL
lock time. The value is also available for reset and changing Power Management Mode.
The setting value can also be valid after 1.5 HCLK. Only, 1HCLK can validate the value of CLKDIVN register changed
from Default (1:1:1) to other Divide Ratio (1:1:2, 1:2:2, 1:2:4 and 1:4:4)
1 HCLK 1.5 HCLK 1.5 HCLK
0x00000000 0x00000001(1:1:2) 0x00000003 (1:2:4) 0x00000000 (1:1:1)
CLKDIVN
FCLK
HCLK
PCLK
Figure 7-6. Changing CLKDIVN Register Value
NOTES
1. CLKDIVN should be set carefully not to exceed the limit of HCLK and PCLK.
2. If HDIVN = 1, the CPU bus mode has to be changed from the fast bus mode to the asynchronous bus
mode using following instructions.
MMU_SetAsyncBusMode
mrc p15,0,r0,c1,c0,0
orr r0,r0,#R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
If HDIVN=1 and the CPU bus mode is the fast bus mode, the CPU will operate by the HCLK. This feature
can be used to change the CPU frequency as a half without affecting the HCLK and PCLK.