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S3C2410A CLOCK & POWER MANAGEMENT
7-19
CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTER
LOCK TIME COUNT REGISTER (LOCKTIME)
Register Address R/W Description Reset Value
LOCKTIME 0x4C000000 R/W PLL lock time count register 0x00FFFFFF
LOCKTIME Bit Description Initial State
U_LTIME [23:12] UPLL lock time count value for UCLK.
(U_LTIME > 150uS)
0xFFF
M_LTIME [11:0] MPLL lock time count value for FCLK, HCLK, and PCLK
(M_LTIME > 150uS)
0xFFF
PLL Control Register (MPLLCON and UPLLCON)
Mpll = (m * Fin) / (p * 2
s
)
m = (MDIV + 8), p = (PDIV + 2), s = SDIV
NOTE: Although there is the rule for choosing PLL value, we recommend only the values in the PLL value
recommendation table. If you have to use another value, please contact us.
Register Address R/W Description Reset Value
MPLLCON 0x4C000004 R/W MPLL configuration register 0x0005C080
UPLLCON 0x4C000008 R/W UPLL configuration register 0x00028080
PLLCON Bit Description Initial State
MDIV [19:12] Main divider control 0x5C / 0x28
PDIV [9:4] Pre-divider control 0x08 / 0x08
SDIV [1:0] Post divider control 0x0 / 0x0
NOTE: When you set MPLL&UPLL values simultaneously, set UPLL value first and then MPLL value. (Needs intervals
approximately 7 NOP)