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MEMORY CONTROLLER S3C2410A
5-12
HCLK
SCKE
nSCS
nSCAS
ADDR
A10/AP
RA
nSRAS
BA
DATA (CL2)
DATA (CL3)
nWE
DQM
Trp
Trcd
RA
Ca
Da
Da
BABA
Cb Cc Cd Ce
Db Dc Dd De
Db Dc Dd De
BA BA BA BA BA
Bank
Precharge
Row
Active
Write Read (CL = 2, CL = 3, BL = 1)
Trp = 2 cycle Tcas = 2 cycle
Trcd = 2 cycle Tcp = 2 cycle
Figure 5-13. S3C2410A SDRAM Timing Diagram