Filter
Top Products
S3C2410A MICROPROCESSOR xxvii
List of Tables
Table Title Page
Number Number
1-1 272-Pin FBGA Pin Assignments – Pin Number Order.............................................1-7
1-2 272-Pin FBGA Pin Assignments...........................................................................1-10
1-3 S3C2410A Signal Descriptions .............................................................................1-20
1-4 S3C2410A Special Registers................................................................................1-26
2-1 PSR Mode Bit Values..........................................................................................2-9
2-2 Exception Entry/Exit............................................................................................2-11
2-3 Exception Vectors...............................................................................................2-13
3-1 The ARM Instruction Set ......................................................................................3-2
3-2 Condition Code Summary.....................................................................................3-4
3-3 ARM Data Processing Instructions........................................................................3-11
3-4 Incremental Cycle Times......................................................................................3-16
3-5 Assembler Syntax Descriptions............................................................................3-27
3-6 Addressing Mode Names .....................................................................................3-45
4-1 THUMB Instruction Set Opcodes ..........................................................................4-3
4-2 Summary of Format 1 Instructions ........................................................................4-5
4-3 Summary of Format 2 Instructions ........................................................................4-7
4-4 Summary of Format 3 Instructions ........................................................................4-9
4-5 Summary of Format 4 Instructions ........................................................................4-11
4-6 Summary of Format 5 Instructions ........................................................................4-13
4-7 Summary of PC-Relative Load Instruction ..............................................................4-16
4-8 Summary of Format 7 Instructions ........................................................................4-19
4-9 Summary of format 8 instructions..........................................................................4-20
4-10 Summary of Format 9 Instructions ........................................................................4-23
4-11 Halfword Data Transfer Instructions .......................................................................4-24
4-12 SP-Relative Load/Store Instructions ......................................................................4-26
4-13 Load Address......................................................................................................4-28
4-14 The ADD SP Instruction.......................................................................................4-30
4-15 PUSH and POP Instructions.................................................................................4-31
4-16 The Multiple Load/Store Instructions......................................................................4-33
4-17 The Conditional Branch Instructions ......................................................................4-34
4-18 The SWI Instruction.............................................................................................4-36
4-19 Summary of Branch Instruction.............................................................................4-37
4-20 The BL Instruction ...............................................................................................4-39
5-1 Bank 6/7 Addresses ............................................................................................5-2
5-2 SDRAM Bank Address Configuration.....................................................................5-4
7-1 Clock Source Selection at Boot-Up.......................................................................7-2
7-2 Clock and Power State in Each Power Mode .........................................................7-10
7-3 CLKSLOW and CLKDIVN Register Settings for SLOW Clock..................................7-11