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LCD CONTROLLER S3C2410A
15-42
Register Setting Guide (TFT LCD)
The CLKVAL register value determines the frequency of VCLK and frame rate.
Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } × {(HSPW+1) + (HBPD +1)
+ (HFPD+1) + (HOZVAL + 1) } × { 2 × ( CLKVAL+1 ) / ( HCLK ) } ]
For applications, the system timing must be considered to avoid under-run condition of the fifo of the lcd controller
caused by memory bandwidth contention.
Example 4:
TFT Resolution: 240 × 240,
VSPW = 2, VBPD = 14, LINEVAL = 239, VFPD = 4
HSPW = 25, HBPD = 15, HOZVAL = 239, HFPD = 1
CLKVAL = 5
HCLK = 60M (Hz)
The parameters below must be referenced by LCD size and driver specifications:
VSPW, VBPD, LINEVAL, VFPD, HSPW, HBPD, HOZVAL, and HFPD
If target frame rate is 60–70Hz, then CLKVAL should be 5.
So, Frame Rate = 67Hz
Known Problems
Problem : In a MDS, such as Multi-ICE, some of the LCD controller registers may be displayed incorrectly in
the memory view window of the ARM debugger.
Solution : The LCD controller register will be displayed correctly unless the memory view window is used.
Instead, use 'pr' command in the debugger console window.