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S3C2410A CLOCK & POWER MANAGEMENT
7-17
Signaling EINT[15:0] for Wakeup
The S3C2410A can be woken up from Power_OFF mode only if the following conditions are met.
a) Level signals (H or L) or edge signals (rising or falling or both) are asserted on EINTn input pin.
b) The EINTn pin has to be configured as EINT in the GPIO control register.
c) nBATT_FLT pin has to be H level. It is important to configure the EINTn in the GPIO control register as an
external interrupt pins, considering the condition a) above.
Just after the wake-up, the corresponding EINTn pin will not be used for wakeup. This means that the pin can be
used as an external interrupt request pin again.
Entering IDLE Mode
If CLKCON[2] is set to 1 to enter the IDLE mode, the S3C2410A will enter IDLE mode after some delay (until the
power control logic receives ACK signal from the CPU wrapper).
PLL On/Off
The PLL can only be turned off for low power consumption in slow mode. If the PLL is turned off in any other mode,
MCU operation is not guaranteed.
When the processor is in SLOW mode and tries to change its state into other state with the PLL turned on, then
SLOW_BIT should be clear to move to another state after PLL stabilization
Pull-up Resistors on the Data Bus and Power_OFF Mode
In Power_OFF mode, the data bus (D[31:0] or D[15:0] ) is in Hi-z state.
But, because of the characteristics of I/O pad, the data bus pull-up resistors have to be turned on for low power
consumption in Power_OFF mode. D[31:0] pin pull-up resistors can be controlled by the GPIO control register
(MISCCR). However, if there is an external bus holder, such as 74LVCH162245, on the data bus, turning off the data
bus pull-up resistors will be reduce power consumption.