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IIC-BUS INTERFACE S3C2410A
20-2
PCLK
Address Register
SDA4-bit Prescaler
IIC-Bus Control Logic
IICSTATIICCON
Comparator
Shift Register
Shift Register
(IICDS)
Data Bus
SCL
Figure 20-1. IIC-Bus Block Diagram
NOTE: IIC DATA HOLD TIME
The IIC data hold time(tSDAH) is minimum 0ns.
(IIC data hold time is minimum 0ns for standard/fast bus mode in IIC specification v2.1.)
Please check the data hold time of your IIC device if it's 0 nS or not.
The IIC controller supports only IIC bus device(standard/fast bus mode), not C bus device.