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ARM920T PROCESSOR PROGRAMMER'S MODEL
2-3
INSTRUCTION SET EXTENSION SPACES
All ARM processors implement the undefined instruction space as one of the entry mechanisms for the undefined
instruction exception. That is, ARM instructions with opcode[27:25] = 0b011 and opcode[4] = 1 are undefined on all
ARM processors including the ARM9TDMI and ARM7TDMI.
ARM architecture v4 and v4T also introduced a number of instruction set extension spaces to the ARM instruction
set. These are:
• arithmetic instruction extension space
• control instruction extension space
• coprocessor instruction extension space
• load/store instruction extension space.
Instructions in these spaces are undefined (they cause an undefined instruction exception). The ARM9TDMI fully
implements all the instruction set extension spaces defined in ARM architecture v4T as undefined instructions,
allowing emulation of future instruction set additions.
The system control coprocessor (CP15) allows configuration and control of the caches, MMU, protection system and
clocking mode of the ARM920T.
The ARM920T coprocessor 15 registers are described under the following sections:
• Accessing CP15 registers on page 2-5
• Register 0: ID code register on page 2-7
• Register 0: Cache type register on page 2-8
• Register 1: Control register on page 2-10
• Register 2: Translation table base (TTB) register on page 2-12
• Register 3: Domain access control register on page 2-13
• Register 4: Reserved on page 2-14
• Register 5: Fault status registers on page 2-14
• Register 6: Fault address register on page 2-15
• Register 7: Cache operations on page 2-15
• Register 8: TLB operations on page 2-18
• Register 9: Cache lock down register on page 2-19
• Register 10: TLB lock down register on page 2-21
• Registers 11 -12 & 14: Reserved on page 2-22
• Register 13: Process ID on page 2-22
• Addresses in ARM920T on page 2-6
• Register 15: Test configuration register on page 2-24.